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https://github.com/LineageOS/android_kernel_samsung_msm8226.git
synced 2026-09-28 00:00:22 +02:00
msm: pm: save registers to noncached area before pc
The power collapse path is simplified if a noncached area is used for the purpose of saving register state prior to power collapsing. This is especially beneficial in the case of targets with an outer cache, where the process of cleaning the register state would require complex operations. Change-Id: I9edac28e4091548e2843fc87c89e3451df2b6ae9 Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
This commit is contained in:
Steve Muckle
committed by
Murali Nalajala
Murali Nalajala
parent
e6a0acd4f3
commit
fcece057c3
+17
-22
@@ -19,13 +19,8 @@
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#include <linux/threads.h>
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#include <asm/assembler.h>
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#ifdef CONFIG_MSM_CPU_AVS
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/* 11 general purpose registers (r4-r14), 10 cp15 registers, 3 AVS registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10 + 4 * 3)
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#else
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/* 11 general purpose registers (r4-r14), 10 cp15 registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10)
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#endif
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#include "idle.h"
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#ifdef CONFIG_ARCH_MSM_KRAIT
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#define SCM_SVC_BOOT 0x1
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#define SCM_CMD_TERMINATE_PC 0x2
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@@ -45,7 +40,8 @@ ENTRY(msm_pm_collapse)
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cpsid f
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#endif
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ldr r0, =saved_state
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ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
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ldr r0, [r0] /* load ptr */
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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@@ -100,14 +96,7 @@ ENTRY(msm_pm_collapse)
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cmp r1, #1
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bne skip
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bl v7_flush_dcache_all
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b skip2
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skip: ldr r0, =saved_state
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ldr r1, =saved_state_end
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sub r1, r1, r0
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bl v7_flush_kern_dcache_area
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skip2:
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skip:
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#ifdef CONFIG_ARCH_MSM_KRAIT
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ldr r0, =SCM_SVC_BOOT
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ldr r1, =SCM_CMD_TERMINATE_PC
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@@ -134,7 +123,8 @@ skip2:
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#ifdef CONFIG_MSM_JTAG
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bl msm_jtag_restore_state
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#endif
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ldr r0, =saved_state /* restore registers */
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ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
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ldr r0, [r0] /* load ptr */
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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@@ -143,7 +133,7 @@ skip2:
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add r0, r0, r2
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#endif
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ldmfd r0, {r4-r14}
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ldmfd r0, {r4-r14} /* restore registers */
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mov r0, #0 /* return power collapse failed */
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bx lr
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@@ -157,11 +147,12 @@ ENTRY(msm_pm_collapse_exit)
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mov r1, #'A'
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str r1, [r0, #0x00C]
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#endif
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ldr r1, =saved_state
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ldr r1, =msm_saved_state_phys
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ldr r2, =msm_pm_collapse_exit
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adr r3, msm_pm_collapse_exit
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add r1, r1, r3
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sub r1, r1, r2
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ldr r1, [r1]
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add r1, r1, #CPU_SAVED_STATE_SIZE
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#if (NR_CPUS >= 2)
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mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
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@@ -277,9 +268,13 @@ ENTRY(msm_pm_set_l2_flush_flag)
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msm_pm_pc_pgd:
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.long 0x0
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saved_state:
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.space CPU_SAVED_STATE_SIZE * NR_CPUS
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saved_state_end:
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.globl msm_saved_state
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msm_saved_state:
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.long 0x0
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.globl msm_saved_state_phys
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msm_saved_state_phys:
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.long 0x0
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msm_pm_boot_vector:
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.space 4 * NR_CPUS
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@@ -14,9 +14,21 @@
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#ifndef _ARCH_ARM_MACH_MSM_IDLE_H_
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#define _ARCH_ARM_MACH_MSM_IDLE_H_
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#ifdef CONFIG_MSM_CPU_AVS
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/* 11 general purpose registers (r4-r14), 10 cp15 registers, 3 AVS registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10 + 4 * 3)
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#else
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/* 11 general purpose registers (r4-r14), 10 cp15 registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10)
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#endif
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#ifndef __ASSEMBLY__
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int msm_arch_idle(void);
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int msm_pm_collapse(void);
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void msm_pm_collapse_exit(void);
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extern void *msm_saved_state;
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extern unsigned long msm_saved_state_phys;
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#ifdef CONFIG_CPU_V7
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void msm_pm_boot_entry(void);
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@@ -38,5 +50,5 @@ static inline void msm_pm_write_boot_vector(unsigned int cpu,
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/* empty */
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}
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#endif
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#endif
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#endif
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@@ -1182,6 +1182,17 @@ static int __init msm_pm_init(void)
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pmd[0] = __pmd(pmdval);
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pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
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msm_saved_state_phys =
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allocate_contiguous_ebi_nomap(CPU_SAVED_STATE_SIZE *
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num_possible_cpus(), 4);
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if (!msm_saved_state_phys)
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return -ENOMEM;
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msm_saved_state = ioremap_nocache(msm_saved_state_phys,
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CPU_SAVED_STATE_SIZE *
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num_possible_cpus());
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if (!msm_saved_state)
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return -ENOMEM;
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/* It is remotely possible that the code in msm_pm_collapse_exit()
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* which turns on the MMU with this mapping is in the
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* next even-numbered megabyte beyond the
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@@ -1879,6 +1879,17 @@ static int __init msm_pm_init(void)
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pmd[0] = __pmd(pmdval);
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pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
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msm_saved_state_phys =
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allocate_contiguous_ebi_nomap(CPU_SAVED_STATE_SIZE *
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num_possible_cpus(), 4);
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if (!msm_saved_state_phys)
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return -ENOMEM;
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msm_saved_state = ioremap_nocache(msm_saved_state_phys,
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CPU_SAVED_STATE_SIZE *
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num_possible_cpus());
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if (!msm_saved_state)
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return -ENOMEM;
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/* It is remotely possible that the code in msm_pm_collapse_exit()
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* which turns on the MMU with this mapping is in the
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* next even-numbered megabyte beyond the
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