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Merge "msm: spm: add intermediate LPM mode for L2 PC"

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2013-10-15 01:32:30 -07:00
committed by Gerrit - the friendly Code Review server
parent d942127b2c 82123b0253
commit 25bc984924
4 changed files with 7 additions and 0 deletions
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Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
+1
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@@ -20,6 +20,7 @@ The required nodes for lpm-levels are:
"pc_no_xo_shutdown" - Power Collapse with no XO shutdown
- qcom,l2: The state of L2 cache. Values are:
"l2_cache_pc" - L2 cache in power collapse
"l2_cache_pc_no_rpm" - L2 cache in power collapse. This mode wouldn't inform the RPM
"l2_cache_retenetion" - L2 cache in retention
"l2_cache_gdhs" - L2 cache in GDHS
"l2_cache_active" - L2 cache in active mode
arch/arm/mach-msm/lpm_levels.c
+4
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@@ -191,6 +191,9 @@ static int msm_lpm_set_l2_mode(int sleep_mode)
case MSM_SPM_L2_MODE_GDHS:
msm_pm_set_l2_flush_flag(MSM_SCM_L2_GDHS);
break;
case MSM_SPM_L2_MODE_PC_NO_RPM:
msm_pm_set_l2_flush_flag(MSM_SCM_L2_OFF);
break;
case MSM_SPM_L2_MODE_RETENTION:
case MSM_SPM_L2_MODE_DISABLED:
break;
@@ -448,6 +451,7 @@ static int msm_lpm_get_l2_cache_value(struct device_node *node,
int i;
struct lpm_lookup_table l2_mode_lookup[] = {
{MSM_SPM_L2_MODE_POWER_COLLAPSE, "l2_cache_pc"},
{MSM_SPM_L2_MODE_PC_NO_RPM, "l2_cache_pc_no_rpm"},
{MSM_SPM_L2_MODE_GDHS, "l2_cache_gdhs"},
{MSM_SPM_L2_MODE_RETENTION, "l2_cache_retention"},
{MSM_SPM_L2_MODE_DISABLED, "l2_cache_active"}
arch/arm/mach-msm/spm.h
+1
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@@ -24,6 +24,7 @@ enum {
MSM_SPM_L2_MODE_DISABLED = MSM_SPM_MODE_DISABLED,
MSM_SPM_L2_MODE_RETENTION,
MSM_SPM_L2_MODE_GDHS,
MSM_SPM_L2_MODE_PC_NO_RPM,
MSM_SPM_L2_MODE_POWER_COLLAPSE,
};
arch/arm/mach-msm/spm_devices.c
+1
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@@ -397,6 +397,7 @@ static int __devinit msm_spm_dev_probe(struct platform_device *pdev)
struct mode_of of_l2_modes[] = {
{"qcom,saw2-spm-cmd-ret", MSM_SPM_L2_MODE_RETENTION, 1},
{"qcom,saw2-spm-cmd-gdhs", MSM_SPM_L2_MODE_GDHS, 1},
{"qcom,saw2-spm-cmd-pc-no-rpm", MSM_SPM_L2_MODE_PC_NO_RPM, 1},
{"qcom,saw2-spm-cmd-pc", MSM_SPM_L2_MODE_POWER_COLLAPSE, 1},
};