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Abhijeet Dharmapurikar
dd167853a8
KPSS version 2.1 introduces a hardware sequencer which executes the necessary steps to switch between BHS and LDO krait power modes. The driver has to set the APC_PWR_GATE_MODE register to initiate a switch between LDO and BHS Krait power modes. Modify the driver to use this hardware sequencer. Also, switch to the V2 SPM sequence with the delays added for HW sequencer to idle. Also, with the V2 sequences, it is expected that APC_PWR_GATE_CTL register be configured once before using the APC_PWR_GATE_MODE register to switch between LDO and BHS. Update the code such that for secondary cpus APC_PWR_GATE_MODE is written to after configuring APC_PWR_GATE_CTL in the secondary_cpu_hs_init() function. Note that secondary_cpu_hs_init() is guaranteed to run only once for each secondary cpu when that core is brought up for the first time. Subsequent hotplug in/out of that core do not take this code execution path. For boot cpu, since it is up and running, its APC_PWR_GATE_CTL should already be initialized. So for boot cpu configure its APC_PWR_GATE_MODE register right at probe time. secondary_cpu_hs_init() isn't invoked for boot cpu. Change-Id: Ie5584c12f47283cad8834ccdb3d4d44c66305a22 Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>