mirror of
https://github.com/LineageOS/android_kernel_samsung_msm8226.git
synced 2026-10-04 00:00:35 +02:00
Jay Chokshi
9d36a3d457
Add support for the Qualcomm PM8038 PMIC chip. The core driver will communicate with the PMIC chip via the MSM SSBI bus. Initial support is provided for: IRQ, GPIO, MPP, RTC, Power Key, Misc, and Debug. Change-Id: I83f995cc238699100a05e82d04b45ea2a63eb667 Signed-off-by: Jay Chokshi <jchokshi@codeaurora.org>
264 lines
8.0 KiB
C
264 lines
8.0 KiB
C
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PM8XXX_MPP_H
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#define __PM8XXX_MPP_H
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#include <linux/errno.h>
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#define PM8XXX_MPP_DEV_NAME "pm8xxx-mpp"
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struct pm8xxx_mpp_core_data {
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int base_addr;
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int nmpps;
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};
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struct pm8xxx_mpp_platform_data {
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struct pm8xxx_mpp_core_data core_data;
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int mpp_base;
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};
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/**
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* struct pm8xxx_mpp_config_data - structure to specify mpp configuration values
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* @type: MPP type which determines the overall MPP function (i.e. digital
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* in/out/bi, analog in/out, current sink, or test). It should be
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* set to the value of one of PM8XXX_MPP_TYPE_D_*.
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* @level: meaning depends upon MPP type specified
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* @control: meaning depends upon MPP type specified
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*
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* Usage of level argument:
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* 1. type = PM8XXX_MPP_TYPE_D_INPUT, PM8XXX_MPP_TYPE_D_OUTPUT,
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* PM8XXX_MPP_TYPE_D_BI_DIR, or PM8XXX_MPP_TYPE_DTEST_OUTPUT -
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*
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* level specifies that digital logic level to use for the MPP. It should
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* be set to the value of one of PM8XXX_MPP_DIG_LEVEL_*. Actual regulator
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* connections for these level choices are PMIC chip specific.
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*
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* 2. type = PM8XXX_MPP_TYPE_A_INPUT -
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*
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* level specifies where in the PMIC chip the analog input value should
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* be routed to. It should be set to the value of one of
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* PM8XXX_MPP_AIN_AMUX_*.
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*
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* 3. type = PM8XXX_MPP_TYPE_A_OUTPUT -
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*
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* level specifies the output analog voltage reference level. It should
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* be set to the value of one of PM8XXX_MPP_AOUT_LVL_*.
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*
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* 4. type = PM8XXX_MPP_TYPE_SINK or PM8XXX_MPP_TYPE_DTEST_SINK -
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*
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* level specifies the output current level. It should be set to the value
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* of one of PM8XXX_MPP_CS_OUT_*.
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*
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* Usage of control argument:
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* 1. type = PM8XXX_MPP_TYPE_D_INPUT -
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*
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* control specifies how the digital input should be routed in the chip.
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* It should be set to the value of one of PM8XXX_MPP_DIN_TO_*.
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*
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* 2. type = PM8XXX_MPP_TYPE_D_OUTPUT -
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*
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* control specifies the digital output value. It should be set to the
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* value of one of PM8XXX_MPP_DOUT_CTRL_*.
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*
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* 3. type = PM8XXX_MPP_TYPE_D_BI_DIR -
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*
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* control specifies the pullup resistor value. It should be set to the
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* value of one of PM8XXX_MPP_BI_PULLUP_*.
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*
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* 4. type = PM8XXX_MPP_TYPE_A_INPUT -
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*
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* control is unused; a value of 0 is sufficient.
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*
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* 5. type = PM8XXX_MPP_TYPE_A_OUTPUT -
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*
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* control specifies if analog output is enabled. It should be set to the
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* value of one of PM8XXX_MPP_AOUT_CTRL_*.
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*
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* 6. type = PM8XXX_MPP_TYPE_SINK -
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*
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* control specifies if current sinking is enabled. It should be set to
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* the value of one of PM8XXX_MPP_CS_CTRL_*.
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*
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* 7. type = PM8XXX_MPP_TYPE_DTEST_SINK -
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*
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* control specifies if current sinking is enabled. It should be set to
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* the value of one of PM8XXX_MPP_DTEST_CS_CTRL_*.
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*
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* 8. type = PM8XXX_MPP_TYPE_DTEST_OUTPUT -
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*
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* control specifies which DTEST bus value to output. It should be set to
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* the value of one of PM8XXX_MPP_DTEST_*.
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*/
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struct pm8xxx_mpp_config_data {
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unsigned type;
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unsigned level;
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unsigned control;
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};
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/* API */
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#if defined(CONFIG_GPIO_PM8XXX_MPP) || defined(CONFIG_GPIO_PM8XXX_MPP_MODULE)
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/**
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* pm8xxx_mpp_config() - configure control options of a multi-purpose pin (MPP)
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* @mpp: global GPIO number corresponding to the MPP
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* @config: configuration to set for this MPP
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* Context: can sleep
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*
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* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
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*/
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int pm8xxx_mpp_config(unsigned mpp, struct pm8xxx_mpp_config_data *config);
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#else
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static inline int pm8xxx_mpp_config(unsigned mpp,
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struct pm8xxx_mpp_config_data *config)
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{
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return -ENXIO;
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}
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#endif
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/* MPP Type: type */
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#define PM8XXX_MPP_TYPE_D_INPUT 0
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#define PM8XXX_MPP_TYPE_D_OUTPUT 1
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#define PM8XXX_MPP_TYPE_D_BI_DIR 2
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#define PM8XXX_MPP_TYPE_A_INPUT 3
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#define PM8XXX_MPP_TYPE_A_OUTPUT 4
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#define PM8XXX_MPP_TYPE_SINK 5
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#define PM8XXX_MPP_TYPE_DTEST_SINK 6
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#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
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/* Digital Input/Output: level */
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#define PM8XXX_MPP_DIG_LEVEL_VIO_0 0
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#define PM8XXX_MPP_DIG_LEVEL_VIO_1 1
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#define PM8XXX_MPP_DIG_LEVEL_VIO_2 2
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#define PM8XXX_MPP_DIG_LEVEL_VIO_3 3
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#define PM8XXX_MPP_DIG_LEVEL_VIO_4 4
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#define PM8XXX_MPP_DIG_LEVEL_VIO_5 5
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#define PM8XXX_MPP_DIG_LEVEL_VIO_6 6
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#define PM8XXX_MPP_DIG_LEVEL_VIO_7 7
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/* Digital Input/Output: level [PM8058] */
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#define PM8058_MPP_DIG_LEVEL_VPH 0
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#define PM8058_MPP_DIG_LEVEL_S3 1
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#define PM8058_MPP_DIG_LEVEL_L2 2
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#define PM8058_MPP_DIG_LEVEL_L3 3
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/* Digital Input/Output: level [PM8901] */
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#define PM8901_MPP_DIG_LEVEL_MSMIO 0
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#define PM8901_MPP_DIG_LEVEL_DIG 1
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#define PM8901_MPP_DIG_LEVEL_L5 2
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#define PM8901_MPP_DIG_LEVEL_S4 3
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#define PM8901_MPP_DIG_LEVEL_VPH 4
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/* Digital Input/Output: level [PM8921] */
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#define PM8921_MPP_DIG_LEVEL_S4 1
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#define PM8921_MPP_DIG_LEVEL_L15 3
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#define PM8921_MPP_DIG_LEVEL_L17 4
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#define PM8921_MPP_DIG_LEVEL_VPH 7
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/* Digital Input/Output: level [PM8821] */
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#define PM8821_MPP_DIG_LEVEL_1P8 1
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#define PM8821_MPP_DIG_LEVEL_VPH 7
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/* Digital Input/Output: level [PM8018] */
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#define PM8018_MPP_DIG_LEVEL_L4 0
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#define PM8018_MPP_DIG_LEVEL_L14 1
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#define PM8018_MPP_DIG_LEVEL_S3 2
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#define PM8018_MPP_DIG_LEVEL_L6 3
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#define PM8018_MPP_DIG_LEVEL_L2 4
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#define PM8018_MPP_DIG_LEVEL_L5 5
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#define PM8018_MPP_DIG_LEVEL_VPH 7
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/* Digital Input/Output: level [PM8038] */
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#define PM8038_MPP_DIG_LEVEL_L20 0
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#define PM8038_MPP_DIG_LEVEL_L11 1
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#define PM8038_MPP_DIG_LEVEL_L5 2
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#define PM8038_MPP_DIG_LEVEL_L15 3
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#define PM8038_MPP_DIG_LEVEL_L17 4
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#define PM8038_MPP_DIG_LEVEL_VPH 7
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/* Digital Input: control */
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#define PM8XXX_MPP_DIN_TO_INT 0
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#define PM8XXX_MPP_DIN_TO_DBUS1 1
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#define PM8XXX_MPP_DIN_TO_DBUS2 2
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#define PM8XXX_MPP_DIN_TO_DBUS3 3
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/* Digital Output: control */
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#define PM8XXX_MPP_DOUT_CTRL_LOW 0
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#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
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#define PM8XXX_MPP_DOUT_CTRL_MPP 2
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#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
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/* Bidirectional: control */
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#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
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#define PM8XXX_MPP_BI_PULLUP_OPEN 1
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#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
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#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
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/* Analog Input: level */
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#define PM8XXX_MPP_AIN_AMUX_CH5 0
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#define PM8XXX_MPP_AIN_AMUX_CH6 1
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#define PM8XXX_MPP_AIN_AMUX_CH7 2
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#define PM8XXX_MPP_AIN_AMUX_CH8 3
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#define PM8XXX_MPP_AIN_AMUX_CH9 4
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#define PM8XXX_MPP_AIN_AMUX_ABUS1 5
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#define PM8XXX_MPP_AIN_AMUX_ABUS2 6
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#define PM8XXX_MPP_AIN_AMUX_ABUS3 7
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/* Analog Output: level */
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#define PM8XXX_MPP_AOUT_LVL_1V25 0
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#define PM8XXX_MPP_AOUT_LVL_1V25_2 1
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#define PM8XXX_MPP_AOUT_LVL_0V625 2
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#define PM8XXX_MPP_AOUT_LVL_0V3125 3
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#define PM8XXX_MPP_AOUT_LVL_MPP 4
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#define PM8XXX_MPP_AOUT_LVL_ABUS1 5
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#define PM8XXX_MPP_AOUT_LVL_ABUS2 6
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#define PM8XXX_MPP_AOUT_LVL_ABUS3 7
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/* Analog Output: control */
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#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
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#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
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#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
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#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
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/* Current Sink: level */
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#define PM8XXX_MPP_CS_OUT_5MA 0
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#define PM8XXX_MPP_CS_OUT_10MA 1
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#define PM8XXX_MPP_CS_OUT_15MA 2
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#define PM8XXX_MPP_CS_OUT_20MA 3
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#define PM8XXX_MPP_CS_OUT_25MA 4
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#define PM8XXX_MPP_CS_OUT_30MA 5
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#define PM8XXX_MPP_CS_OUT_35MA 6
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#define PM8XXX_MPP_CS_OUT_40MA 7
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/* Current Sink: control */
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#define PM8XXX_MPP_CS_CTRL_DISABLE 0
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#define PM8XXX_MPP_CS_CTRL_ENABLE 1
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#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
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#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
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/* DTEST Current Sink: control */
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#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
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#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
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#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
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#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
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/* DTEST Digital Output: control */
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#define PM8XXX_MPP_DTEST_DBUS1 0
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#define PM8XXX_MPP_DTEST_DBUS2 1
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#define PM8XXX_MPP_DTEST_DBUS3 2
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#define PM8XXX_MPP_DTEST_DBUS4 3
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#endif
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