mirror of
https://github.com/LineageOS/android_kernel_samsung_msm8226.git
synced 2026-10-04 00:00:35 +02:00
Subhash Jadavani
8f13e5b3e4
When SW writes to MCI_POWER, MCI_CLK, MCI_CMD and MCI_DATA_CTL registers, the register write operation is completed after 3HCLK + 2 MCLK clock cycles. SW should access these registers only after the register write operation is completed. This synchronization delay can't be ignored, especially in case the MCLK is slow (e.g. 400 KHz). Special status bit is defined to wait properly for register write completion bit MCLK_REG_WR_ACTIVE of MCI_STATUS2 register. SW should always wait until bit MCLK_REG_WR_ACTIVE of MCI_STATUS2 register is low after writing to one of mentioned above registers and before accessing them again. Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>