The current check on Ion heaps is too restrictive. It assumes that
all heaps specified with a base address (implying it is a carveout
like heap) must have memory removed with memblock_remove. This is
not a valid assumption. Newer memory managment techniques such
as CMA will not remove memory from the memblock. Ensuring that
memory is properly removed can and should be done elsewhere.
Remove this check entirely.
Change-Id: If2ef1fe2b7f1d3e34c7f48a1a48d2f566d916f93
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
When allocating pages that are intended to be used for
uncached allocations, we need to ensure the cache is coherent;
there may be outstanding data in the cache related to those
pages. Ensure cache coherency by flushing each of the pages.
Change-Id: I4b89c799b5c099f6c050d8ddd758bdb368c07c08
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
We remove an incorrect check for currently active context.
The intent of the original check was to ensure that the
current context is at least there/valid before we issue
a dummy command with a forced interrupt. However, this
check was implemented incorrectly, instead of checking
the context under which the function is running, the check
was probing the "drawctxt_active" which may not necessarily
be the same as the context for which the function was called.
We fix this by changing the check to instead look for the
context under which the kgsl_check_interrupt_timestamp() has
been called.
CRs-fixed: 426186
Change-Id: I6ac123d16888287b14e6e53028f482eb709f24c5
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
Log a ftrace event when the GPU statistics are collected so that
we can keep track of GPU busy along with the other statistics
in the ftrace stream.
Change-Id: Ic0dedbadb58b9bef6e8669a7634bf9ca87073bcb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
A3XX doesn't have the MH block and so the register at 0x40 points
somewhere else. Luckily the write was harmless but remove it anyway.
Change-Id: Ic0dedbadd1e043cd38bbaec8fcf0c490dcdedc8c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
It is interesting to know when and how we program the hardware so
add a tracepoint to monitor register writes. Register reads are
not traced since they are done much more frequently and are somewhat
less interesting from a debug perspective.
Change-Id: Ic0dedbad8ee85f154b9ba8731fe2c14603351243
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
kgsl_pwrctrl_pwrlevel_change might be called when clocks are on or off.
If clocks are off we don't step the clock rate and the active_pwrlevel
won't be set to the new and correct level. Set active_pwrlevel to its
new level before doing anything else.
Change-Id: Ic0dedbad84ce1cc1b3b8df97df32e39686b85671
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Extend the cp heap to allow memory to be allocated from
the contiguous memory allocator (CMA) instead of from
the standard carveout region. The option to use CMA or regular
carveout memory is configured via a parameter in platform
data.
Change-Id: Ie26a867f8355280b4086afd7631a934a7c4b1e21
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
A number of changes have been made to the Ion framework for the
msm target. Add the necessary changes on top of the CMA heap to
allow the CMA heap to be fully utilized.
Change-Id: Ie006dcd4c41481e4d914c67bafbf42d1afdb1a76
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
map_kernel and unmap_kernel in kmalloc_ops should support
a contiguous heap. The existing functions
ion_system_heap_map_kernel and ion_system_heap_unmap_kernel
are geared towards discontiguous memory (supported via
vmalloc_ops) and crash while handling contiguous heaps. This
patch adds two new functions specific to contiguous system
heaps to initialize kmalloc_ops.
Change-Id: I48d30ca01c5a0b71af4e1e640c79a920a298aedb
Acked-by: Jennifer L. Zenner <jzenner@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Reading the A3XX HLSQ registers during a GPU hang recovery might cause
the device to hang. Disable the the HLSQ register reads that would
cause recovery to fail until the failures are better understood.
Change-Id: I1553025fbd824bfacf91f062372d5731cd905cc4
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Disable clock gating earlier when recording the GPU snapshot.
This will ensure that there are no issues when reading register
values from the GPU hardware.
Change-Id: I173655b419c958f0b8cdfa4609c712e512ff2487
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
New heap type ION_HEAP_TYPE_DMA where allocation is done with dma_alloc_coherent API.
device coherent_dma_mask must be set to DMA_BIT_MASK(32).
ion_platform_heap private field is used to retrieve the device linked to CMA,
if NULL the default CMA area is used.
ion_cma_get_sgtable is a copy of dma_common_get_sgtable function which should
be in kernel 3.5
Change-Id: I9ae54a3a021cb3513c2b0e8c58b69f3ae118561b
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
[lauraa: Fix context in ion_priv.h/ion.h and omit Makefile change for now]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
copy private field from platform configuration to internal heap structure.
Change-Id: Ia7571d88fc2f72f5d655fb6f6b54fde389d96c85
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
[laura: Rebase context fixes]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
fix ion_platform_heap to make is use an usual way in board configuration file.
Change-Id: I8686108a9fe0aa2ba9f9c84990d555f947f78f86
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
[lauraa: Fixup msm board files]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
When trying to add commands to the ringbuffer command stream, ensure
that the context point is not NULL before dereferencing it.
Change-Id: I6d8217ed4b180454eb43f2db161c10e86bc207da
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
KGSL_GPUMEM_ALLOC_ID now takes a flag,
KGSL_MEMFLAGS_USE_CPU_MAP. When set, the GPU
mapping will be set up to match the CPU mapping
during mmap(). This feature is only supported when
using per process pagetables with the IOMMU. The
flags field of KGSL_GPUMEM_ALLOC_ID is copied back
to userspace and KGSL_MEMFLAGS_USE_CPU_MAP will
be cleared when this feature is not supported.
The IOMMU virtual address space has been adjusted
when perprocess pagetables is enabled so that the
entire userpace address range (0 to TASK_SIZE) can
have equivalent mappings on the IOMMU. For buffers
that do not have equivalent mappings, the address
range from PAGE_OFFSET to KGSL_IOMMU_GLOBAL_MEM_BASE
is used.
Change-Id: Ib61c03aa7453c3dd901c41e8fd297f66d402ae1a
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
The user allocating memory can provide hints for the caching
settings when said buffer is mapped on the user side. Try
to obey the cache settings when applicable. The user will
be responsible for handling cache management both to and
from the GPU so add a new ioctl IOCTL_KGSL_GPUMEM_CACHE_SYNC to
support both directions (the old IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE)
only handled flushing, not invalidating. The legacy ioctl still
works it just does what it says it does - a cache flush.
Change-Id: Ic0dedbad55ce82f2b01ebc56de30d4649e2e7311
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Previously, the gpu address has been used to uniquely
identify each memory allocation. Upcoming patches will
introduce cases where an allocation does not always
have a gpu address, so an additional id is needed.
IOCTL_KGSL_GPUMEM_ALLOC_ID allocates pages and returns
an id.
IOCTL_KGSL_GPUMEM_FREE_ID frees an id. KGSL_SHAREDMEM_FREE
can still be used to free by GPU address, if it exists.
The id can also be passed to mmap(), shifted left by
PAGE_SIZE to get a CPU mapping for the buffer.
IOCTL_KGSL_GPUMEM_ALLOC_GET_INFO can be called to retrieve
the id and other information about the buffer.
Change-Id: I4b45f0660cb9d4a5fb1323ccc6c4aa360791c1ec
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
When GPU resumes from suspend requested state is not cleared to NONE.
Due to this idle reporting is not done and GPU stays at MAX freq. As
a fix if the current power state is already ACTIVE and request is
made for active power state then clear the requested state immediately.
CRs-fixed: 424682
Change-Id: I7f0d7fa819308f166cbbbf30b2c20aee73644cfb
Signed-off-by: Vinay Roy <vroy@codeaurora.org>
Add min_pwrlevel, max_pwrlevel and thermal_pwrlevel to give a
privileged user more control over which power levels are considered
during DCVS power management. max_pwrlevel is the maximum power
level that the system can go to at any time, min_pwrlevel represents
the lowest power level. DCVS will chose any level between these
two extremes. thermal_pwrlevel allows a daemon to set an absolute
top for frequency to prevent thermal issues. The effective maximum
power level is considered to be the lower of thermal or max.
Also added is num_pwrlevels that shows the number of active power
levels. This corresponds to the gpu frequencies in
available_gpu_frequencies.
Change-Id: Ic0dedbad20102d9a3c3350055e6fcd10358fc53d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add separate kernel memory mapping for GPU shader memory.
Previously, both the register and the shader memory were mapped
as one entity, with the mapping length being equal to combined
size of register memory and shader memory. Now, we separate the
shader memory mapping to help in cases of GPU devices where the
shader and register memory may not be adjacent. This helps to
dump the shader memory in the postmortem snapshot. By having a
separate mapping for shader memory, the snapshot dump routine
simply reads in the shader memory range specified and dumps.
Change-Id: I30e59dffe849fefcfbbaf0e5245cc1024ccedcb1
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
Clock registers hold critical information of clock state that is
crucial for hang analysis. Dump this information as part of postmortem
dump.
Change-Id: I210bdd087e1844d1485caa1712239fdcb4f38982
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Adding extra cache flush command to make sure that CP block
gets event from RB all the time to avoid race conditions because of
clock switches. this is to improve stability on 8x25 target.
Change-Id: Ie411be46fa166864073d35c50085a8f2506d0eb8
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
The interrupts added to the ringbuffer on PTFLUSH and TLBUPDATE
were causing a major increase in the number of interrupts from the GPU.
This was leading to increase in power and loss of performance. Add a check
to turn off IOMMU clocks when going to SLEEP.
Change-Id: I41617dd3b7b3f7d9622523f2a1407b912dbd989e
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
The adreno core needs to know what the next event pending for
any given context is so it can mark the interupt to be fired.
If this isn't done then some timestamps that don't have a
matching waittimestamp call won't fire an interrupt. This is
dangerous on the last interrupt/event before a context goes
away.
Change-Id: Ic0dedbad71f6de07b43b0656128c76509326d645
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We have always allowed the user to specify a timeout in waittimestamp
but we never obeyed it. Reorganize the function to be less convoluted
and support a user specified timeout (or spin forever if 0 is passed).
Change-Id: Ic0dedbadbc368336d05b14d66829205631046515
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Sometimes a write to CP_WPTR fails to latch on A20x GPUs. In the past
we worked around this by writing to WPTR numerous times in the various
loops that waited for GPU activity. Consolidate these disparate calls
by moving the poke into the hang detect function. If the core is idle
but the RPTR != WPTR, then rewrite the WPTR and go back through the
loop again.
Change-Id: Ic0dedbad474c7884c2467fe050d8afe673588add
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
System performance is enhanced if the gpu frequency is given a
minimum corresponding to various frequency levels of CPU 0.
Change-Id: Iba168d708524fc8ef164428bb5f4e0631a499342
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
