As per eMMC specification, the PON (Power Off Notification)
must be sent by host to the card before turning off the power.
This will allow card to prepare itself for the power off and
may even reduce the initialization of eMMC upon next boot-up.
Send long PON during system power off and send short PON during
system reboot to reduce the reboot latency.
Change-Id: If4188b8b80aaa0e6c4e00e1807aa9589d5e7efdb
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Use the correct power class field from the extended CSD register
for HS400 mode as defined in the eMMC5.0 specification.
CRs-fixed: 690341
Change-Id: Ie10e35941fd3c6ee49c686f721bf5af6fcd74862
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
As of now we ignore CRC/INDEX command failures to tuning command
and still wait for data from card but in case the card did not
receive the command, it won't send the data. This is causing
software request timeout for tuning commands. Hence, software
must not ignore such cmd errors for tuning commands but end the
request immediately after resetting the controller for both CMD
and DATA. Also, wait for 146 MCLK cycles for card to send out the
data and thus to move to transfer state. Its corresponding phase must
also be considered as bad phase.
CRs-fixed: 625855
Change-Id: Ic8462dd9c67e4f18a3ce73d972591772be8c6d10
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This change prevents enabling cache during card init for specific
Kingstone card.
This change is workaround the problem of long timeouts for cache
operations.
CRs-Fixed: 625480
Change-Id: I6be53a408c7d6422556585d4ea2f9b1c487563e0
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
eMMC and SD card specifications restrict the usage of a class of
commands while commands in other class are in progress. For example,
during erase operations the SD/eMMC spec. allows only CMD35, CMD36,
CMD38. If clock scaling is enabled and decide to scale up the clocks
it may be possible that CMD19/21 tuning commands are sent in between
erase commands, which is illegal as per specification.
Fix such illegal transactions to the card and also make clock scaling
statistics accountable only for read/write commands instead of time
consuming commands, like CMD38 erase, where transactions are independent
of bus frequency.
Change-Id: Iffba175787837e7f95bde8970f19d0f0f9d7d67d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Get the various drive types other than the default supported
by the card.
Change-Id: I122971e4fb4a3ab98f0078ceafca3380e9c0e2d1
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.
CRs-Fixed: 585481
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch initializes wakeup source if the detected card
is a sdio card and enables the wakeup capability.
Platform drivers would have to invoke:
* pm_wakeup_event on this card device to signal a wakeup
* corresponding pm_relax have to be invoked
CRs-Fixed: 585481
Change-Id: Ic8d5c98073e8ed3f676eb42fc0ce1f13a11cb40f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Some controllers can gate the clock to save power
even for SDIO cards. In such cases, an asynchronous
interrupt mechanism is used to receive interrupts
even when clocks are off.
This patch wakes up the sdio thread if interrupts
were received when clocks were off.
CRs-Fixed: 585481
Change-Id: Ifcfafad251dedc992637596b6bb9349cfbca5d8b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This change prevents enabling cache during card init for Hynix cards.
This change is workaround the problem of Hynix cards behavior for
adb reboot flow, when as a result of power cycle with cache enabled,
ext4 journal get aborted, because of meta data corruption.
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Conflicts:
drivers/mmc/card/block.c
include/linux/mmc/card.h
Change-Id: I721689da65e803965f1c7dd148754c4f19a64857
Signed-off-by: Maya Erez <merez@codeaurora.org>
Add a quirk to increase the data-timeout value for Hynix eMMC
cards only. This value is fixed to a maximum of 4 seconds.
Change-Id: I4bca6cbc877b323b29a3f7f5923d0708c48adf2c
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Fix buffer overflow while caching the mmc ext_csd content.
Also, to avoid duplicate allocation keep the allocated ext_csd
till the card is removed.
CRs-Fixed: 583929
Change-Id: I5d69e37f6fd1f5249479d454c353be050df40b6d
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
There is currently no mechanism to disable the runtime-pm
of eMMC/SD card. This patch adds the mechanism to disable
runtime-pm of eMMC/SD if MMC_CAP2_CORE_RUNTIME_PM is not
defined.
It sets the platform, class and card device as RPM_ACTIVE
irrespective of the capability but doesn't enable it.
The card is never runtime-suspended and hence the
corresponding mmc_host and platform device are not
runtime-suspended as well.
A capability MMC_CAP2_CORE_PM is used to select the use
of core power-management framework.
CRs-Fixed: 490021
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Change-Id: I394a81a889ab7d4f0f0e6fe4b932630e30fc16c9
As per specification, auto cmd error status register is valid only
when auto cmd error bit is set in Error interrupt status register.
CRs-fixed: 515513
Change-Id: Id1013e1705d8efdba0171dcad14f783607d38ef3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This patch adds clock scaling support to HS400 cards.
Scaling down to 52MHz from HS400 involves:
- switching the bus-speed mode to HS at 52MHz
Scaling up to HS400 would require all of the initialization
process upto HS400 mode selection.
Change-Id: I8196d6666bcc0ef327659253df53a17792fa51f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
There is race between sdhci_tasklet_finish()
and sdhci_stop_request(): when the request is finished before
stop flow called, error returned.
Change-Id: Ic036feae925b2e9e5435e44f97b24a179547bf49
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Certain Hynix eMMC 4.41 cards might get broken when HPI feature is used
and hence this patch disables the HPI feature for such buggy cards.
As some of the other features like BKOPs/Cache/Sanitize are dependent on
HPI feature, those features would also get disabled if HPI is disabled.
Change-Id: I6a638ce089cbd977122e47aecb721bc3f0adf7b0
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
HS400 bus speed mode also requires tuning to be performed as done in
HS200 mode. Add the capability in host layer to perform tuning for
HS400 too.
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
HS400 is a new bus speed mode introduced in eMMC5.0 specification. This
patch adds the capability in mmc core to switch to HS400 mode when both
the host and the card supports it.
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The bus speed selection code in mmc_card_init() is convoluted, refactor
the code to simplify this and make it simpler for adding new bus speed
capabilities.
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.
Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.
In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.
CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
When the card is removed in mmc_sd_detect(), the card status is
marked as runtime suspended and this asynchronously triggers
runtime suspend of it's parent mmc_host class device. The
mmc_power_off() will be called from runtime suspend handler and
it races with mmc_power_off() within mmc_sd_detect(). Fix this by
acquiring mutex at the host driver when set_ios host operation
is invoked and until it is done.
CRs-fixed: 513141
Change-Id: I4e7afbe966ecbcc2c8bf746fb6cffc64b7cf252e
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
As "bkops_busy" flag is no longer used, remove it from the mmc_command
structure.
Change-Id: Icd405ba4879c5dfc915eba9bf821633fdd87fbb6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Some of the time consuming operations such as BKOPS, SANITIZE, CACHE
flush/off use the SWITCH command (CMD6) but as these operations don't
have card specification defined timeout for completion, we may see
timeout errors if card doesn't complete the operation within the SW
defined timeout. If SW defined timeout is hit, above operations are
considered to be failed and no real recovery mechanism is implemented
after timeout.
Most of the above operations (BKOPS/SANITIZE/CACHE flush/off) can be
interrupted by sending the HPI (High Priority Interrupt) command to card
if they taking longer than expected. This change adds the base support
which will these operations to be HPIed after timeout.
Change-Id: Ibd9061525756aaae656b1ceeeaed62e04fb80cce
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
To handle card-detect of SD/MMC slot pins we need generic flags to
specify their polarity.
Change-Id: I8d71ec888931e7ec6adaac9a5623c003dde78a87
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
At the moment only POWER_OFF_SHORT is sent to the device in case the host
is suspended. This patch adds the support of sending POWER_OFF_LONG
notification in case the device is powered off.
According to device vendors the POWER_OFF_LONG notification will shorten
the initialization time of the eMMC card during next boot up.
Change-Id: I3c6f224398450cf10463cbb316613fd430d1e8d2
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
MMC Host driver might want to use the mmc_host_may_gate_card() API
to know whether the clock can be gated to the card or not hence
export this function for usage outside its current scope.
Change-Id: I9ec4173063e2505eca179161cdf8cda033a3fd4b
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off. Host needs
to first read the "Support Asynchronous Interrupt" bit in CCCR register
space to check if the card supports the feature or not. If yes and if
the host wants to enable the feature, host needs to write '1' to
"Enable Asynchronous Interrupt" bit in CCCR register space.
This change allows the host controller driver to control whether to enable
the asynchronous interrupt in card or not and if the asynchronous interrupt
is enabled then clock gating feature would be enabled for such cards.
Change-Id: I678cffb63af6a2013640a5eafa6ce9bfad8a51d6
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The original intention of polling for BKOPS completion was to give
the card enough time to perform the BKOPS before it is runtime suspended.
But as the BKOPS completion polling was happening in a different
context, it may race with card runtime/platform suspend which is quite
difficult to fix. So instead of BKOPS polling, let the runtime suspend
get deferred if the BKOPS is running on the card. Also if BKOPS is running
when platform suspend is triggered, stop the BKOPS before suspending the
card.
CRs-Fixed: 489523
Change-Id: I21e524dc2da37c4985c210abfaca00a28049c651
Signed-off-by: Maya Erez <merez@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Host drivers can participate in clock scaling by registering
->notify_load host operation, which allows host driver to carry out
platform specific operations for further power savings or increasing
throughput based on whether load is LOW or HIGH respectively. This
can be applicable to non-ultra high speed cards as well so remove
the check for ultra high speed cards to initialize clock scaling.
Change-Id: Icaab9520135e384f5470db68b2f25c5cdce5663a
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The MSM SDHCI controller defines the usage of 0xF in data
timeout counter register (0x2E) which is actually a reserved
bit as per specification. This would result in maximum of
5.3 secs timeout value. For some buggy SD cards, the core
layer wants to set the data timeout to 3 secs and on our MSM
SDHCI if we configure data timeout counter value to 0xE,
then we would get only 2.67 secs. Observed data timeout errors
for CMD25 on SDR104 card. Hence program data timeout counter to
0xF, to achieve at least 3 secs timeout value.
CRs-fixed: 470661
Change-Id: Ie1e192eb9c38ca3922bb1f518073a8ff0cb57f0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This helps check the controller timeout logic in case of data
timeout errors.
Change-Id: Ia30757192e49865698c5f52940e1dc5d97746185
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If preset value (bit 15) is enabled in sdhci host control2
register (0x3E), then the preset value registers(0x6F-0x60)
would be used for some of the settings such as clock and
drive strength. These are HW initialized registers and are
not properly initialized by MSM SDHCI controller. This is
resulting in low throughput for some of the modes such as
DDR50/SDR50. Hence, do not enable it for MSM SDHCI.
CRs-fixed: 474518
Change-Id: Iee1241355d14e6bcebc66c3a43abf1ec94d869c3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Ignore data timeout error for R1B commands as there will be no
data associated and the busy timeout value for these commands
could be lager than the maximum timeout value that controller
can handle.
CRs-fixed: 473435
Change-Id: I61f7463cf09648ad9fab83437abf5004effc7758
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
mmc_signal_sdio_irq() should only be called when the function
driver registers for IRQ notification. In case, if any host
driver recieves a spurious interrupt and call mmc_signal_sdio_irq(),
ignore waking up uninitialized sdio irq thread.
CRs-Fixed: 472609
Change-Id: I831717fe80918538a18cc1f2300fe7fe2817c70f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Francescodario Cuzzocrea
Sahitya Tummala
Venkat Gopalakrishnan
Konstantin Dorfman
Sujit Reddy Thumma
Linux Build Service Account
Krishna Konda
Asutosh Das
Maya Erez
Pratibhasagar V
Subhash Jadavani
Tatyana Brokhman