forked from rubenslte/android_kernel_samsung_msm8226
raghavendra ambadas
ff7c49624a
Add mutex lock betweeen mhl_sii_config and mhl_sii_device_discovery functions to avoid accesing the variable flag before it is updated. This will avoid accessing the mhl init settings i2c register before turning on the mhl regulator's and gpio's. Change-Id: If3f7fbe3d6ab84f101c407c43ac8b410e6df38fe Signed-off-by: Raghavendra Ambadas <rambad@codeaurora.org>
382 lines
13 KiB
C
382 lines
13 KiB
C
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MHL_MSM_H__
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#define __MHL_MSM_H__
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <mach/board.h>
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#include <linux/mhl_devcap.h>
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#include <linux/power_supply.h>
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#include <linux/mhl_defs.h>
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#define MHL_DEVICE_NAME "sii8334"
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#define MHL_DRIVER_NAME "sii8334"
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#define HPD_UP 1
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#define HPD_DOWN 0
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enum discovery_result_enum {
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MHL_DISCOVERY_RESULT_USB = 0,
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MHL_DISCOVERY_RESULT_MHL,
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};
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struct msc_command_struct {
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u8 command;
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u8 offset;
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u8 length;
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u8 retry;
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union {
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u8 data[16];
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u8 *burst_data;
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} payload;
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u8 retval;
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};
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struct scrpd_struct {
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u8 offset;
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u8 length;
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u8 data[MHL_SCRATCHPAD_SIZE];
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};
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/* MHL 8334 supports a max HD pixel clk of 75 MHz */
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#define MAX_MHL_PCLK 75000
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/* USB driver interface */
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#if defined(CONFIG_FB_MSM_HDMI_MHL_8334)
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/* mhl_device_discovery */
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extern int mhl_device_discovery(const char *name, int *result);
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/* - register|unregister MHL cable plug callback. */
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extern int mhl_register_callback
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(const char *name, void (*callback)(int online));
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extern int mhl_unregister_callback(const char *name);
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#else
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static inline int mhl_device_discovery(const char *name, int *result)
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{
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return -ENODEV;
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}
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static inline int
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mhl_register_callback(const char *name, void (*callback)(int online))
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{
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return -ENODEV;
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}
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static inline int mhl_unregister_callback(const char *name)
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{
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return -ENODEV;
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}
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#endif
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struct msc_cmd_envelope {
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/*
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* this list head is for list APIs
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*/
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struct list_head msc_queue_envelope;
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struct msc_command_struct msc_cmd_msg;
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};
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struct mhl_msm_state_t {
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struct i2c_client *i2c_client;
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struct i2c_driver *i2c_driver;
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uint8_t cur_state;
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uint8_t chip_rev_id;
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struct msm_mhl_platform_data *mhl_data;
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/* Device Discovery stuff */
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int mhl_mode;
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struct completion rgnd_done;
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struct completion msc_cmd_done;
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uint16_t devcap_state;
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uint8_t path_en_state;
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struct work_struct mhl_msc_send_work;
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struct list_head list_cmd;
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void (*msc_command_put_work) (struct msc_command_struct *);
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struct msc_command_struct* (*msc_command_get_work) (void);
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};
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#ifdef CONFIG_FB_MSM_MDSS_HDMI_MHL_SII8334
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enum mhl_gpio_type {
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MHL_TX_RESET_GPIO,
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MHL_TX_INTR_GPIO,
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MHL_TX_PMIC_PWR_GPIO,
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MHL_TX_MAX_GPIO,
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};
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enum mhl_vreg_type {
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MHL_TX_3V_VREG,
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MHL_TX_MAX_VREG,
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};
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struct mhl_tx_platform_data {
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/* Data filled from device tree nodes */
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struct dss_gpio *gpios[MHL_TX_MAX_GPIO];
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struct dss_vreg *vregs[MHL_TX_MAX_VREG];
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int irq;
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struct platform_device *hdmi_pdev;
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};
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struct mhl_tx_ctrl {
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struct platform_device *pdev;
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struct mhl_tx_platform_data *pdata;
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struct i2c_client *i2c_handle;
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uint8_t cur_state;
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uint8_t chip_rev_id;
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int mhl_mode;
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struct completion rgnd_done;
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void (*notify_usb_online)(void *ctx, int online);
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void *notify_ctx;
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struct usb_ext_notification *mhl_info;
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bool disc_enabled;
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struct power_supply mhl_psy;
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bool vbus_active;
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int current_val;
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struct completion msc_cmd_done;
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uint8_t devcap[16];
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uint16_t devcap_state;
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uint8_t status[2];
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uint8_t path_en_state;
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uint8_t tmds_en_state;
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void *hdmi_mhl_ops;
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struct work_struct mhl_msc_send_work;
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struct list_head list_cmd;
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struct input_dev *input;
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struct workqueue_struct *msc_send_workqueue;
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struct workqueue_struct *mhl_workq;
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struct work_struct mhl_intr_work;
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u16 *rcp_key_code_tbl;
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size_t rcp_key_code_tbl_len;
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struct scrpd_struct scrpd;
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int scrpd_busy;
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int wr_burst_pending;
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struct completion req_write_done;
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spinlock_t lock;
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/*
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* Lock between mhl_sii_config and
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* mhl_sii_device_discovery functions
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*/
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struct mutex sii_config_lock;
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bool tx_powered_off;
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uint8_t dwnstream_hpd;
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bool mhl_det_discon;
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bool irq_req_done;
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};
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int mhl_i2c_reg_read(struct i2c_client *client,
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uint8_t slave_addr_index, uint8_t reg_offset);
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int mhl_i2c_reg_write(struct i2c_client *client,
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uint8_t slave_addr_index, uint8_t reg_offset,
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uint8_t value);
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void mhl_i2c_reg_modify(struct i2c_client *client,
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uint8_t slave_addr_index, uint8_t reg_offset,
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uint8_t mask, uint8_t val);
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#endif /* CONFIG_FB_MSM_MDSS_HDMI_MHL_SII8334 */
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enum {
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TX_PAGE_TPI = 0x00,
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TX_PAGE_L0 = 0x01,
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TX_PAGE_L1 = 0x02,
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TX_PAGE_2 = 0x03,
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TX_PAGE_3 = 0x04,
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TX_PAGE_CBUS = 0x05,
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TX_PAGE_DDC_EDID = 0x06,
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TX_PAGE_DDC_SEGM = 0x07,
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};
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enum mhl_st_type {
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POWER_STATE_D0_NO_MHL = 0,
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POWER_STATE_D0_MHL = 2,
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POWER_STATE_D3 = 3,
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};
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enum {
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DEV_PAGE_TPI_0 = (0x72),
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DEV_PAGE_TX_L0_0 = (0x72),
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DEV_PAGE_TPI_1 = (0x76),
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DEV_PAGE_TX_L0_1 = (0x76),
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DEV_PAGE_TX_L1_0 = (0x7A),
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DEV_PAGE_TX_L1_1 = (0x7E),
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DEV_PAGE_TX_2_0 = (0x92),
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DEV_PAGE_TX_2_1 = (0x96),
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DEV_PAGE_TX_3_0 = (0x9A),
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DEV_PAGE_TX_3_1 = (0x9E),
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DEV_PAGE_CBUS = (0xC8),
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DEV_PAGE_DDC_EDID = (0xA0),
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DEV_PAGE_DDC_SEGM = (0x60),
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};
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#define MHL_SII_PAGE0_RD(off) \
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mhl_i2c_reg_read(client, TX_PAGE_L0, off)
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#define MHL_SII_PAGE0_WR(off, val) \
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mhl_i2c_reg_write(client, TX_PAGE_L0, off, val)
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#define MHL_SII_PAGE0_MOD(off, mask, val) \
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mhl_i2c_reg_modify(client, TX_PAGE_L0, off, mask, val)
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#define MHL_SII_PAGE1_RD(off) \
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mhl_i2c_reg_read(client, TX_PAGE_L1, off)
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#define MHL_SII_PAGE1_WR(off, val) \
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mhl_i2c_reg_write(client, TX_PAGE_L1, off, val)
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#define MHL_SII_PAGE1_MOD(off, mask, val) \
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mhl_i2c_reg_modify(client, TX_PAGE_L1, off, mask, val)
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#define MHL_SII_PAGE2_RD(off) \
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mhl_i2c_reg_read(client, TX_PAGE_2, off)
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#define MHL_SII_PAGE2_WR(off, val) \
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mhl_i2c_reg_write(client, TX_PAGE_2, off, val)
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#define MHL_SII_PAGE2_MOD(off, mask, val) \
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mhl_i2c_reg_modify(client, TX_PAGE_2, off, mask, val)
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#define MHL_SII_PAGE3_RD(off) \
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mhl_i2c_reg_read(client, TX_PAGE_3, off)
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#define MHL_SII_PAGE3_WR(off, val) \
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mhl_i2c_reg_write(client, TX_PAGE_3, off, val)
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#define MHL_SII_PAGE3_MOD(off, mask, val) \
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mhl_i2c_reg_modify(client, TX_PAGE_3, off, mask, val)
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#define MHL_SII_CBUS_RD(off) \
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mhl_i2c_reg_read(client, TX_PAGE_CBUS, off)
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#define MHL_SII_CBUS_WR(off, val) \
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mhl_i2c_reg_write(client, TX_PAGE_CBUS, off, val)
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#define MHL_SII_CBUS_MOD(off, mask, val) \
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mhl_i2c_reg_modify(client, TX_PAGE_CBUS, off, mask, val)
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#define REG_SRST ((TX_PAGE_3 << 16) | 0x0000)
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#define REG_INTR1 ((TX_PAGE_L0 << 16) | 0x0071)
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#define REG_INTR1_MASK ((TX_PAGE_L0 << 16) | 0x0075)
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#define REG_INTR2 ((TX_PAGE_L0 << 16) | 0x0072)
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#define REG_TMDS_CCTRL ((TX_PAGE_L0 << 16) | 0x0080)
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#define REG_DISC_CTRL1 ((TX_PAGE_3 << 16) | 0x0010)
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#define REG_DISC_CTRL2 ((TX_PAGE_3 << 16) | 0x0011)
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#define REG_DISC_CTRL3 ((TX_PAGE_3 << 16) | 0x0012)
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#define REG_DISC_CTRL4 ((TX_PAGE_3 << 16) | 0x0013)
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#define REG_DISC_CTRL5 ((TX_PAGE_3 << 16) | 0x0014)
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#define REG_DISC_CTRL6 ((TX_PAGE_3 << 16) | 0x0015)
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#define REG_DISC_CTRL7 ((TX_PAGE_3 << 16) | 0x0016)
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#define REG_DISC_CTRL8 ((TX_PAGE_3 << 16) | 0x0017)
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#define REG_DISC_CTRL9 ((TX_PAGE_3 << 16) | 0x0018)
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#define REG_DISC_CTRL10 ((TX_PAGE_3 << 16) | 0x0019)
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#define REG_DISC_CTRL11 ((TX_PAGE_3 << 16) | 0x001A)
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#define REG_DISC_STAT ((TX_PAGE_3 << 16) | 0x001B)
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#define REG_DISC_STAT2 ((TX_PAGE_3 << 16) | 0x001C)
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#define REG_INT_CTRL ((TX_PAGE_3 << 16) | 0x0020)
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#define REG_INTR4 ((TX_PAGE_3 << 16) | 0x0021)
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#define REG_INTR4_MASK ((TX_PAGE_3 << 16) | 0x0022)
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#define REG_INTR5 ((TX_PAGE_3 << 16) | 0x0023)
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#define REG_INTR5_MASK ((TX_PAGE_3 << 16) | 0x0024)
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#define REG_MHLTX_CTL1 ((TX_PAGE_3 << 16) | 0x0030)
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#define REG_MHLTX_CTL2 ((TX_PAGE_3 << 16) | 0x0031)
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#define REG_MHLTX_CTL3 ((TX_PAGE_3 << 16) | 0x0032)
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#define REG_MHLTX_CTL4 ((TX_PAGE_3 << 16) | 0x0033)
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#define REG_MHLTX_CTL5 ((TX_PAGE_3 << 16) | 0x0034)
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#define REG_MHLTX_CTL6 ((TX_PAGE_3 << 16) | 0x0035)
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#define REG_MHLTX_CTL7 ((TX_PAGE_3 << 16) | 0x0036)
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#define REG_MHLTX_CTL8 ((TX_PAGE_3 << 16) | 0x0037)
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#define REG_TMDS_CSTAT ((TX_PAGE_3 << 16) | 0x0040)
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#define REG_CBUS_INTR_STATUS ((TX_PAGE_CBUS << 16) | 0x0008)
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#define REG_CBUS_INTR_ENABLE ((TX_PAGE_CBUS << 16) | 0x0009)
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#define REG_DDC_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000B)
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#define REG_CBUS_BUS_STATUS ((TX_PAGE_CBUS << 16) | 0x000A)
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#define REG_PRI_XFR_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000D)
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#define REG_CBUS_PRI_FWR_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000E)
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#define REG_CBUS_PRI_START ((TX_PAGE_CBUS << 16) | 0x0012)
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#define REG_CBUS_PRI_ADDR_CMD ((TX_PAGE_CBUS << 16) | 0x0013)
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#define REG_CBUS_PRI_WR_DATA_1ST ((TX_PAGE_CBUS << 16) | 0x0014)
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#define REG_CBUS_PRI_WR_DATA_2ND ((TX_PAGE_CBUS << 16) | 0x0015)
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#define REG_CBUS_PRI_RD_DATA_1ST ((TX_PAGE_CBUS << 16) | 0x0016)
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#define REG_CBUS_PRI_RD_DATA_2ND ((TX_PAGE_CBUS << 16) | 0x0017)
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#define REG_CBUS_PRI_VS_CMD ((TX_PAGE_CBUS << 16) | 0x0018)
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#define REG_CBUS_PRI_VS_DATA ((TX_PAGE_CBUS << 16) | 0x0019)
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#define REG_CBUS_MSC_RETRY_INTERVAL ((TX_PAGE_CBUS << 16) | 0x001A)
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#define REG_CBUS_DDC_FAIL_LIMIT ((TX_PAGE_CBUS << 16) | 0x001C)
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#define REG_CBUS_MSC_FAIL_LIMIT ((TX_PAGE_CBUS << 16) | 0x001D)
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#define REG_CBUS_MSC_INT2_STATUS ((TX_PAGE_CBUS << 16) | 0x001E)
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#define REG_CBUS_MSC_INT2_ENABLE ((TX_PAGE_CBUS << 16) | 0x001F)
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#define REG_MSC_WRITE_BURST_LEN ((TX_PAGE_CBUS << 16) | 0x0020)
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#define REG_MSC_HEARTBEAT_CONTROL ((TX_PAGE_CBUS << 16) | 0x0021)
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#define REG_MSC_TIMEOUT_LIMIT ((TX_PAGE_CBUS << 16) | 0x0022)
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#define REG_CBUS_LINK_CONTROL_1 ((TX_PAGE_CBUS << 16) | 0x0030)
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#define REG_CBUS_LINK_CONTROL_2 ((TX_PAGE_CBUS << 16) | 0x0031)
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#define REG_CBUS_LINK_CONTROL_3 ((TX_PAGE_CBUS << 16) | 0x0032)
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#define REG_CBUS_LINK_CONTROL_4 ((TX_PAGE_CBUS << 16) | 0x0033)
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#define REG_CBUS_LINK_CONTROL_5 ((TX_PAGE_CBUS << 16) | 0x0034)
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#define REG_CBUS_LINK_CONTROL_6 ((TX_PAGE_CBUS << 16) | 0x0035)
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#define REG_CBUS_LINK_CONTROL_7 ((TX_PAGE_CBUS << 16) | 0x0036)
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#define REG_CBUS_LINK_STATUS_1 ((TX_PAGE_CBUS << 16) | 0x0037)
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#define REG_CBUS_LINK_STATUS_2 ((TX_PAGE_CBUS << 16) | 0x0038)
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#define REG_CBUS_LINK_CONTROL_8 ((TX_PAGE_CBUS << 16) | 0x0039)
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#define REG_CBUS_LINK_CONTROL_9 ((TX_PAGE_CBUS << 16) | 0x003A)
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#define REG_CBUS_LINK_CONTROL_10 ((TX_PAGE_CBUS << 16) | 0x003B)
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#define REG_CBUS_LINK_CONTROL_11 ((TX_PAGE_CBUS << 16) | 0x003C)
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#define REG_CBUS_LINK_CONTROL_12 ((TX_PAGE_CBUS << 16) | 0x003D)
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#define REG_CBUS_LINK_CTRL9_0 ((TX_PAGE_CBUS << 16) | 0x003A)
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#define REG_CBUS_LINK_CTRL9_1 ((TX_PAGE_CBUS << 16) | 0x00BA)
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#define REG_CBUS_DRV_STRENGTH_0 ((TX_PAGE_CBUS << 16) | 0x0040)
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#define REG_CBUS_DRV_STRENGTH_1 ((TX_PAGE_CBUS << 16) | 0x0041)
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#define REG_CBUS_ACK_CONTROL ((TX_PAGE_CBUS << 16) | 0x0042)
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#define REG_CBUS_CAL_CONTROL ((TX_PAGE_CBUS << 16) | 0x0043)
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#define REG_CBUS_SCRATCHPAD_0 ((TX_PAGE_CBUS << 16) | 0x00C0)
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#define REG_CBUS_DEVICE_CAP_0 ((TX_PAGE_CBUS << 16) | 0x0080)
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#define REG_CBUS_DEVICE_CAP_1 ((TX_PAGE_CBUS << 16) | 0x0081)
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#define REG_CBUS_DEVICE_CAP_2 ((TX_PAGE_CBUS << 16) | 0x0082)
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#define REG_CBUS_DEVICE_CAP_3 ((TX_PAGE_CBUS << 16) | 0x0083)
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#define REG_CBUS_DEVICE_CAP_4 ((TX_PAGE_CBUS << 16) | 0x0084)
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#define REG_CBUS_DEVICE_CAP_5 ((TX_PAGE_CBUS << 16) | 0x0085)
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#define REG_CBUS_DEVICE_CAP_6 ((TX_PAGE_CBUS << 16) | 0x0086)
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#define REG_CBUS_DEVICE_CAP_7 ((TX_PAGE_CBUS << 16) | 0x0087)
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#define REG_CBUS_DEVICE_CAP_8 ((TX_PAGE_CBUS << 16) | 0x0088)
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#define REG_CBUS_DEVICE_CAP_9 ((TX_PAGE_CBUS << 16) | 0x0089)
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#define REG_CBUS_DEVICE_CAP_A ((TX_PAGE_CBUS << 16) | 0x008A)
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#define REG_CBUS_DEVICE_CAP_B ((TX_PAGE_CBUS << 16) | 0x008B)
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#define REG_CBUS_DEVICE_CAP_C ((TX_PAGE_CBUS << 16) | 0x008C)
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#define REG_CBUS_DEVICE_CAP_D ((TX_PAGE_CBUS << 16) | 0x008D)
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#define REG_CBUS_DEVICE_CAP_E ((TX_PAGE_CBUS << 16) | 0x008E)
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#define REG_CBUS_DEVICE_CAP_F ((TX_PAGE_CBUS << 16) | 0x008F)
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#define REG_CBUS_SET_INT_0 ((TX_PAGE_CBUS << 16) | 0x00A0)
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#define REG_CBUS_SET_INT_1 ((TX_PAGE_CBUS << 16) | 0x00A1)
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#define REG_CBUS_SET_INT_2 ((TX_PAGE_CBUS << 16) | 0x00A2)
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#define REG_CBUS_SET_INT_3 ((TX_PAGE_CBUS << 16) | 0x00A3)
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#define REG_CBUS_WRITE_STAT_0 ((TX_PAGE_CBUS << 16) | 0x00B0)
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#define REG_CBUS_WRITE_STAT_1 ((TX_PAGE_CBUS << 16) | 0x00B1)
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#define REG_CBUS_WRITE_STAT_2 ((TX_PAGE_CBUS << 16) | 0x00B2)
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#define REG_CBUS_WRITE_STAT_3 ((TX_PAGE_CBUS << 16) | 0x00B3)
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#define GET_PAGE(x) ((x) >> 16)
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#define GET_OFF(x) ((x) & 0xffff)
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#define MHL_SII_REG_NAME_RD(arg)\
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mhl_i2c_reg_read(client, GET_PAGE(arg), GET_OFF(arg))
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#define MHL_SII_REG_NAME_WR(arg, val)\
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mhl_i2c_reg_write(client, GET_PAGE(arg), GET_OFF(arg), val)
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#define MHL_SII_REG_NAME_MOD(arg, mask, val)\
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mhl_i2c_reg_modify(client, GET_PAGE(arg), GET_OFF(arg), mask, val)
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#endif /* __MHL_MSM_H__ */
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