forked from rubenslte/android_kernel_samsung_msm8226
Saravana Kannan
4bbc993b17
The MSM CPUfreq devfreq governor determines the CPU to DDR bandwidth vote based on the current CPU frequency of all the active CPUs. This functionality used to be a part of the MSM CPUfreq driver that directly voted for the CPU to DDR bandwidth using MSM bus scaling APIs. This refactor decouples CPU to DDR BW scaling from CPU frequency and allows switch between various CPU BW governors. The bandwidth values in the msm-cpufreq table have to be updated since the new CPU BW driver does the MBps to Bps conversion correctly. The MSM CPUfreq driver used to do * 1000 * 1000 to convert from MBps to Bps instead of doing * 1024 * 1024. Change-Id: I184f09d628a1b27d52506d2f760d65831f1a1110 Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
98 lines
3.6 KiB
Plaintext
98 lines
3.6 KiB
Plaintext
menuconfig PM_DEVFREQ
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bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
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help
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A device may have a list of frequencies and voltages available.
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devfreq, a generic DVFS framework can be registered for a device
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in order to let the governor provided to devfreq choose an
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operating frequency based on the device driver's policy.
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Each device may have its own governor and policy. Devfreq can
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reevaluate the device state periodically and/or based on the
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notification to "nb", a notifier block, of devfreq.
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Like some CPUs with CPUfreq, a device may have multiple clocks.
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However, because the clock frequencies of a single device are
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determined by the single device's state, an instance of devfreq
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is attached to a single device and returns a "representative"
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clock frequency of the device, which is also attached
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to a device by 1-to-1. The device registering devfreq takes the
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responsiblity to "interpret" the representative frequency and
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to set its every clock accordingly with the "target" callback
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given to devfreq.
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When OPP is used with the devfreq device, it is recommended to
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register devfreq's nb to the OPP's notifier head. If OPP is
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used with the devfreq device, you may use OPP helper
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functions defined in devfreq.h.
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if PM_DEVFREQ
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comment "DEVFREQ Governors"
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config DEVFREQ_GOV_SIMPLE_ONDEMAND
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tristate "Simple Ondemand"
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help
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Chooses frequency based on the recent load on the device. Works
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similar as ONDEMAND governor of CPUFREQ does. A device with
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Simple-Ondemand should be able to provide busy/total counter
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values that imply the usage rate. A device may provide tuned
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values to the governor with data field at devfreq_add_device().
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config DEVFREQ_GOV_PERFORMANCE
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tristate "Performance"
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help
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Sets the frequency at the maximum available frequency.
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This governor always returns UINT_MAX as frequency so that
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the DEVFREQ framework returns the highest frequency available
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at any time.
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config DEVFREQ_GOV_POWERSAVE
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tristate "Powersave"
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help
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Sets the frequency at the minimum available frequency.
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This governor always returns 0 as frequency so that
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the DEVFREQ framework returns the lowest frequency available
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at any time.
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config DEVFREQ_GOV_USERSPACE
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tristate "Userspace"
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help
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Sets the frequency at the user specified one.
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This governor returns the user configured frequency if there
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has been an input to /sys/devices/.../power/devfreq_set_freq.
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Otherwise, the governor does not change the frequnecy
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given at the initialization.
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config DEVFREQ_GOV_MSM_ADRENO_TZ
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tristate "MSM Adreno Trustzone"
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depends on MSM_KGSL && MSM_SCM
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help
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Trustzone based governor for the Adreno GPU.
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Sets the frequency using a "on-demand" algorithm.
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This governor is unlikely to be useful for other devices.
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config DEVFREQ_GOV_MSM_CPUFREQ
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bool "MSM CPUfreq"
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depends on CPU_FREQ_MSM
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help
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MSM CPUfreq based governor for CPU bandwidth voting. Sets the CPU
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to DDR BW vote based on the current CPU frequency. This governor
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is unlikely to be useful for non-MSM devices.
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comment "DEVFREQ Drivers"
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config ARM_EXYNOS4_BUS_DEVFREQ
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bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
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depends on CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
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select ARCH_HAS_OPP
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select DEVFREQ_GOV_SIMPLE_ONDEMAND
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help
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This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
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and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
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It reads PPMU counters of memory controllers and adjusts
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the operating frequencies and voltages with OPP support.
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To operate with optimal voltages, ASV support is required
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(CONFIG_EXYNOS_ASV).
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endif # PM_DEVFREQ
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