forked from rubenslte/android_kernel_samsung_msm8226
Lorenzo Pieralisi
b4a7906f6f
ARM v7 architecture introduced the concept of cache levels and related control registers. New processors like A7 and A15 embed an L2 unified cache controller that becomes part of the cache level hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable do not require a flush of the entire cache hierarchy to DRAM but just the cache levels belonging to the Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems correspond to L1. The current cache flushing API used in cpu_suspend and __cpu_disable, flush_cache_all(), ends up flushing the whole cache hierarchy since for v7 it cleans and invalidates all cache levels up to Level of Coherency (LoC) which cripples system performance when used in hot paths like hotplug and cpuidle. Therefore a new kernel cache maintenance API must be added to cope with latest ARM system requirements. This patch adds flush_cache_louis() to the ARM kernel cache maintenance API. This function cleans and invalidates all data cache levels up to the Level of Unification Inner Shareable (LoUIS) and invalidates the instruction cache for processors that support it (> v7). This patch also creates an alias of the cache LoUIS function to flush_kern_all for all processor versions prior to v7, so that the current cache flushing behaviour is unchanged for those processors. v7 cache maintenance code implements a cache LoUIS function that cleans and invalidates the D-cache up to LoUIS and invalidates the I-cache, according to the new API. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Change-Id: I561c3b187b5b87b25de07ea82a4ef73a42761e27 Signed-off-by: Karthik Parsha <kparsha@codeaurora.org> Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
148 lines
2.9 KiB
C
148 lines
2.9 KiB
C
/*
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* arch/arm/include/asm/glue-cache.h
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*
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* Copyright (C) 1999-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_GLUE_CACHE_H
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#define ASM_GLUE_CACHE_H
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#include <asm/glue.h>
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/*
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* Cache Model
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* ===========
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*/
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_CACHE_V3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v3
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
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defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
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defined(CONFIG_CPU_ARM1026)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_FA526)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE fa
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM926T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm926
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM940T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm940
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM946E)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm946
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4WB)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4wb
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# endif
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#endif
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#if defined(CONFIG_CPU_XSCALE)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xscale
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# endif
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#endif
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#if defined(CONFIG_CPU_XSC3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xsc3
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# endif
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#endif
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#if defined(CONFIG_CPU_MOHAWK)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE mohawk
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# endif
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#endif
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#if defined(CONFIG_CPU_FEROCEON)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v6
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//# endif
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#endif
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#if defined(CONFIG_CPU_V7)
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//# ifdef _CACHE
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# define MULTI_CACHE 1
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//# else
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//# define _CACHE v7
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//# endif
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#endif
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#if !defined(_CACHE) && !defined(MULTI_CACHE)
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#error Unknown cache maintenance model
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#endif
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#ifndef MULTI_CACHE
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#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
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#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
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#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
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#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
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#define dmac_map_area __glue(_CACHE,_dma_map_area)
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#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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#endif
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#endif
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